By Ali Hurson
Этот свежий сборник знакомит с последними достижениями в архитектуре компьютеров.
Register-Level conversation in Speculative Chip Multiprocessors
Survey on method I/O Transactions and impression on Latency, Throughput, and different Factors
Hardware and alertness Profiling Tools
Model Transformation utilizing Multiobjective Optimization
Manual Parallelization as opposed to cutting-edge Parallelization strategies: The SPEC CPU2006 as a Case examine
Read or Download Advances in Computers, Volume 92 PDF
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Extra resources for Advances in Computers, Volume 92
The register communication is intended to incur minimal additional hardware complexity while keeping the communication latency as low as possible. It avoids complex multiported shared register files, the additional banks of registers for saving the correct values, the prediction schemes, the demanding communication mechanisms, and additional bits for keeping track of the register status. The technique includes both producer- and consumer-initiated communication of the register values. It not only is implemented in hardware but also relies on some off-line software support.
The LC state indicates that a valid register value is the only copy across all processor cores. The register-level communication is carried on over a dedicated shared bus. It encompasses address lines for a register address, data lines for register values, and some control lines. The control part includes BusR, BusW, Mask, and Shared signals. BusR signal denotes the bus read transaction caused by a processor read request for a register in the INV state. The read request is issued on the bus along with the mask code in order to get the requested register value.
The read request for this register is issued on the bus along with the mask code of its speculative thread. Consequently, read miss incurs a consumer-initiated interthread communication. All possible suppliers, that is, predecessors (nonspeculative thread and/or earlier speculative threads) that have a requested register in either the VS or LC state, reply with posting their mask codes on the bus and a distributed arbitrator chooses the nearest predecessor. 21 Processor-initiated state transitions (solid lines) and bus-induced state transitions (dashed lines) for loop-live registers in the SIC protocol.